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Found: 73      Displaying: 21 - 40
#
Part:
Description:
Manuf.
Package
Pins
T°min
T°max
PDF size
21.
HD74ACT107Dual J-K Flip-Flops with Clear
HIT
DP-14
-
-
-
57K
22.
MC74ACT109DDual JK Positive Edge Triggered Flip Flop
ON
SOIC
16
-
-
197K
23.
MC74ACT109DR2Dual JK Positive Edge Triggered Flip Flop
ON
SOIC
16
-
-
197K
24.
MC74ACT109DR2Dual JK Positive Edge Triggered Flip Flop
ON
SOIC
16
-
-
197K
25.
MC74ACT109MDual JK Positive Edge Triggered Flip Flop
ON
-
-
-
-
197K
26.
MC74ACT109ML1Dual JK Positive Edge Triggered Flip Flop
ON
-
-
-
-
197K
27.
MC74ACT109ML2Dual JK Positive Edge Triggered Flip Flop
ON
-
-
-
-
197K
28.
MC74ACT109MR2Dual JK Positive Edge Triggered Flip Flop
ON
-
-
-
-
197K
29.
MC74ACT109NDual JK Positive Edge Triggered Flip Flop
ON
PDIP
16
-
-
197K
30.
MC74ACT10DTriple 3 Input NAND Gate
ON
SOIC
14
-
-
128K
31.
MC74ACT10DR2Triple 3 Input NAND Gate
ON
SOIC
14
-
-
128K
32.
MC74ACT10DTTriple 3 Input NAND Gate
ON
TSSOP
14
-
-
128K
33.
MC74ACT10MTriple 3 Input NAND Gate
ON
SOICEIAJ
14
-
-
128K
34.
SN74ACT1071D 10-BIT BUS TERMINATION NETWORKS WITH BUS HOLD FUNCTION
TI
D
14
-40°C
85°C
58K
35.
SN74ACT1073DW 16-BIT BUS TERMINATION NETWORKS WITH BUS HOLD FUNCTION
TI
DW
20
-40°C
85°C
58K
36.
SN74ACT1073DWR 16-BIT BUS TERMINATION NETWORKS WITH BUS HOLD FUNCTION
TI
DW
20
-40°C
85°C
58K
37.
SN74ACT1073DWR 16-BIT BUS TERMINATION NETWORKS WITH BUS HOLD FUNCTION
TI
DW
20
-40°C
85°C
58K
38.
SN74ACT1073DWR 16-BIT BUS TERMINATION NETWORKS WITH BUS HOLD FUNCTION
TI
DW
20
-40°C
85°C
58K
39.
SN74ACT10PWR TRIPLE 3-INPUT POSITIVE-NAND GATES
TI
PW
14
-40°C
85°C
79K
40.
SN74ACT10PWR TRIPLE 3-INPUT POSITIVE-NAND GATES
TI
PW
14
-40°C
85°C
79K
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